Computer systems consist of one or more processors, each of which executes a collection of machine instructions. The processors may be physical components implemented in semiconductor chips or may be virtual, implemented by operations on one or more physical processors.
Some of the instructions executed by a processor may be performed entirely within the processor. Though, other instructions may entail interaction between the processor and other components of the computer system. Frequently, computer systems will contain separate devices with which the processors will interact as the computer operates. For example, memory operations may entail interactions with a hard disk and network communication operations may entail interaction with a network interface card.
To facilitate these interactions, a computer system may have a bus that supports communication between a processor and other devices. One common type of bus is known as the PCI (Peripheral Component Interconnect) bus. In addition to allowing data to be exchanged, some buses support messages that can signal an interrupt. A device may use such a message to signal to a processor that it has completed an operation requested by the processor or that it has otherwise performed some action or detected a condition that requires service from a processor. In this way, a processor can assign an operation to a device and perform other functions while the device is performing the operation.
Once the device finishes the operation, a processor is notified by the interrupt and may perform completion processing on the operation. The nature of completion processing may vary based on the device or operation performed. Examples of completion processing include reading data from the device or delivering retrieved data to an application that requested the data.
Buses implemented according to the PCI, PCI-X, or PCI Express standard support the message signaled interrupt (MSI) and the message signaled interrupt extended (MSI-X) protocols. Devices that use these protocols may request service by writing a system specified data value to the system specified address using a PCI memory write transaction. System software initializes the message address and message data during device configuration. The message address encodes information on the target processors and delivery mode. The device performs a memory write for a pre-configured MSI message to interrupt the processor.
As is known by those skilled in the art, significant processor overhead is required in processing each interrupt. Accordingly, various interrupt coalescing techniques have been developed in order to reduce the total overhead in performing completion processing, or other interrupt-related processing, on multiple operations. These interrupt coalescing techniques involve sending an interrupt message notifying a processor that multiple operations have been performed and are ready for completion processing. The message event, which could be completion, could be sent in response to a predetermined number of operations, in combination with expiration of a predetermined time period.